AT24C08 DATASHEET PDF

The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. In addition, the entire family is available in 5. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. In addition, the entire family is available in 5. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.

As many as eight 2K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section. The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system.

The A0 pin is a no connect. The AT24C08A only uses the A2 input for hardwire addr es si ng a nd a total of two 8K de vi ces ma y be addressed on a single bus system. The A0 and A1 pins are no connects. Random word addressing requires a 9 bit data word address. Random word addressing requires a 10 bit data word address. STA tSU. STA tHD. DAT tSU. Data changes during SCL high periods will indicate a start or stop condition as defined below. This happens during the ninth clock cycle.

The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. These 3 bits must compare to their corresponding hard-wired input pins. The two device address bits must compare to their corresponding hard-wired input pins. The A0 pin is no connect. The A2 bit must compare to its corresponding hard-wired input pin.

The A1 and A0 pins are no connect. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If a compare is not made, the chip will return to a standby state. The data word address lower three 2K or four 4K, 8K bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page.

This involves sending a start condition followed by the device address word. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.

There are three read operations: current address read, random address read and sequential read. This address stays valid between operations as long as the chip power is maintained.

The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page.

The microcontroller does not respond with an input zero but does generate a following stop condition refer to Figure 4. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.

The microcontroller does not respond with a zero but does generate a following stop condition refer to Figure 5. Following receipt of the 8 bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in.

The microcontroller must terminate the page write sequence with a stop condition refer to Figure 3. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word Figure 1. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition refer to Figure 6.

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AT24C08 DATASHEET PDF

This involves sending a start condition followed by the device address word. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. There are three read operations: current address read, random address read and sequential read. This address stays valid between operations as long as the chip power is maintained. The microcontroller does not respond with an input zero but does generate a following stop condi- tion see Figure 10 on page

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